1. Field of the Invention
The present invention relates to temperature sensitive chips and in particular to a technique to isolate thermal shutdown from current limit shutdown.
2. Related Art
A current limit circuit is typically provided in an integrated circuit (IC) to protect a power device in the IC as well as the external load the IC is driving from excessive current. Typically, a standard current limit circuit monitors the current through a portion (1-2%) of the power device to determine if excessive current is present (e.g. 150 mA to 1.5 A). Note that a power device, e.g. Ea power device forming part of a voltage regulator, is schematically shown as a single transistor. However, the power device is actually implemented using thousands or even tens of thousands of transistors.
As a result, a short circuit in the power device, which is relatively common (because the output of the power device is provided to a pin of the IC, which can be easily, but erroneously, connected to ground instead of a load), can generate a high local temperature. Unfortunately, although a current limit circuit can detect a short circuit, sometimes the local temperature rises so quickly that it can damage circuitry before the current limit circuit can react. Thus, a voltage regulator (or even other circuitry if the IC is small and unable to efficiently dissipate the heat) can be easily damaged due to overheating during a short circuit.
To solve this problem, a thermal shutdown circuit can be positioned near the voltage regulator. FIG. 1 illustrates a standard thermal shutdown circuit 100 including NPN transistors 101 and 104, PMOS transistors 103 and 106, an NMOS transistor 108, and resistors 102 and 105. In this embodiment, resistor 102 can be connected between an emitter of NPN transistor 101 and voltage source VSS (e.g. ground). Similarly, resistor 105 can be connected between an emitter of NPN transistor 104 and VSS. The base of NPN transistor 104 can be connected to the emitter of NPN transistor 101. Note that the collector of NPN transistor 101 can be connected to other circuitry providing a high voltage (not shown for simplicity).
The sources of PMOS transistors 103 and 106 can be connected to a voltage source VDD. The gates of PMOS transistors 103 and 106 can be commonly connected to the drain of PMOS transistor 103 and the collector of NPN transistor 104. The drain of PMOS transistor 106 can be connected to the drain of NMOS transistor 108, wherein the source of NMOS transistor 108 can be connected to VSS.
In thermal shutdown circuit 100, a voltage VB can be applied at the base of NPN transistor 101. The voltage VB is equal to the difference between a bandgap voltage VBG, which can be generated by a bandgap voltage circuit, and a base to emitter voltage VBE (i.e. VB=VBG−VBE). NMOS transistor 108 receives a gate bias voltage Vg1, which moderately turns on NMOS transistor 108. A node 107 provides the FAULT signal of thermal shutdown circuit 100.
In thermal shutdown circuit 100, at a predetermined temperature defining a thermal shutdown (e.g. over 140° C.), voltage VBE is decreased enough to turn on NPN transistor 101. With NPN transistor 101 conducting, a high voltage is also provided to the base of NPN transistor 104, thereby turning on that transistor as well.
When conducting, NPN transistor 104 pulls down the voltage at the drain of PMOS transistor, and thus also pulls down the voltage at the gates of PMOS transistors 103 and 106. This low voltage turns on PMOS transistors 103 and 106, thereby allowing a current I to flow through PMOS transistors 103 and 106, which form a current mirror.
Therefore, during a thermal shutdown in which PMOS transistor 106 is conducting (if only briefly), thereby overcoming the relatively weak pull down provided by NMOS transistor 108, node 107 receives a high voltage, thereby generating a high FAULT signal. This high FAULT signal triggers an IC shutdown. As a result, the IC can quickly shut down if a short circuit occurs.
Unfortunately, if thermal shutdown circuit 200 is proximate to the voltage regulator (and thus the power device), then the thermal shutdown circuit can improperly function during normal operation. Specifically, the VBE of NPN transistors 101 and 104 at room temperature is approximately 0.7 V. However, as the local temperature increases, which is typical in a power device during normal operation, the VBE voltage decreases. For example, at a temperature of approximately 135° C., which is less than the defined thermal shutdown trigger at 140° C., the VBE may decrease to 0.4 V, thereby allowing NPN transistors 101 and 104 to turn on even though a thermal shutdown should not be triggered.
Therefore, a need arises for an efficient thermal shutdown system, which can accurately detect both a local overheat condition as well as a chip overheat condition.